The IIS Chip Gallery

Zorro (2013)

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by

Philipp Dunst, Michael Hutter, Michael Muehlberghuber

Main Details

Application	Cryptography
Technology	180
Manufacturer	UMC
Type	Master Thesis
Package	QFN56
Dimensions	1525μm x 1525μm
Gates	50 kGE
Voltage	1.8 V
Power	1 mW, 1MHz 1.8V
Clock	200 MHz

Description

Zorro was designed to evaluate different counter measures against Differential Power Analysis Attacks (DPAs). Three different implementation are combined on one chip. Therefore, the chip can run in several modes of operation:

• Normal mode: The en- or decryption is performed without any counter measures.
• Masked mode: The operation is secured with secret sharing.
• Hiding mode: The calculation is performed in a normal way but there are additional hiding operations performed.
• Secure masked mode: Secret sharing and hiding operations are combined.

Zorro was designed to compare and evaluate state of the art DPA countermeasure techniques. It contains three independent implementations of an authenticated encryption system. It is based on the Keccak permutation and the duplex construction. It uses a state of 1600 bits and can observe 1024 bits each round. The implementations differ only because of the secret sharing process. They are called

• 3-Share,
• 3-Share-Star
• 4-Share implementation
All features are implemented on all three instances. In addition, each unit is able to perform hiding operations. Hence, another counter measure can be evaluated with the help of Zorro. Those two methods can be combined as well. All together Zorro can run in 12 different modes, excluding test modes

This is another chip that has been designed as part of our long standing collaboration with the IAIK of TU-Graz

.

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