Additional pictures below, click to see larger versions
by
Main Details
| Application | Cryptography |
| Technology | 65 |
| Manufacturer | UMC |
| Type | Semester Thesis |
| Package | QFN56 |
| Dimensions | 2626μm x 1252μm |
| Gates | 1 MGE |
| Voltage | 1.2 V |
| Power | 380 mW @1.2V 300MHz |
| Clock | 405 MHz |
Description
This chip contains 5 candidates for the CAESAR competition to determine an Authenticated Encryption with Associated Data (AEAD) standard. The included candidates are:
- AEGIS-128L
- MORUS-1280-128
- YAES128v2
- TIAOXIN-346
- ICEPOLE-128
As well as an implementation of AES-GCM which is commonly used today for implementing authenticated encryption. All implementations have been geared towards a 100 Gb/s throughput. For testing purposes the top level design of the chip selectively allows to feed candidates from an externally accessible on-chip RAM or from pseudo-randomly generated data. Furthermore clock-gating is used for exact power measurements. This is the second chip that contains candidates for the CAESAR competition, the previous one being CronorX. The long name of the chip is My Little Crypto, Throughput is Magic a play on the popular toy/game/cartoon My Little Pony by Hasbro.
Related Publication
No related publications yet
