The IIS Chip Gallery
Tsukiji (2018)
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| Application | Machine-learning |
| Technology | 65 |
| Manufacturer | UMC |
| Type | Semester Thesis |
| Package | QFN40 |
| Dimensions | 1252μm x 1252μm |
| Gates | 12 |
| Voltage | 1.2 V |
| Power | 1.97 mW @ 0.8V, 156 MHz |
| Clock | 400 MHz |
Tsukiji is a self-contained accelerator which can carry out all operations needed in most binarized convolutional neural networks (BNNs). The reduced arithmetic complexity and particularly the massively reduced storages requirements for intermediate results ask for a rethinking of previous CNN accelerators under these new requirements. By keeping intermediate data in the chip between layers of the CNN, it can spare much of the energy which its competitors spend on IO bandwidth to access external memory, to store the output of each layer. The accelerator achieves a peak core energy efficiency of 95 TOp/s/W, a throughput of 244 GOp/s, and an area efficiency of 2.0 TOp/s/MGE, running at 156 MHz and 0.8 V. In the high performance corner (476 MHz, 1.2V), it performs 746 GOp/s at 32 mW and an energy efficiency of 23.3 TOp/s/W.
The name comes from the time Andy and Geethan presented this chip;s architecture in a conference in Tokio, and were amazed by the experience of the Tsukiji fishing market.