The IIS Chip Gallery

PLINK (2019)

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by

Hayate Okuhara, Ahmed Gamal Mohamed Mahmoud, Davide Rossi

Main Details

Application	Pulp
Technology	65
Manufacturer	UMC
Type	Semester Thesis
Package	QFN56
Dimensions	2626μm x 1252μm
Gates	1 MGE
Voltage	1.2 V
Power	1 pW @ 1.2 V, 1 GHz mW
Clock	1 MHz

Description

PLINK, short for PULP link is a small test chip that will test a serial I/O integrated with a small PULP system. This chip is a collaboration with University of Bologna.

Related Publication

• Hayate Okuhara, Ahmed Elnaqib, Martino Dazzi, Pierpaolo Plestri, Simone Benatti, Luca Benini, Davide Rossi, "A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 10, pp. 1800-1811, Oct. 2021, DOI: 10.1109/TVLSI.2021.3108806