The IIS Chip Gallery
Zest (2021)
Additional pictures below, click to see larger versions
by
| Application | Pulp |
| Technology | 65 |
| Manufacturer | TSMC |
| Type | Research |
| Package | QFN88 |
| Dimensions | 4000μm x 3000μm |
| Gates | 6 MGE |
| Voltage | 1.2 V |
| Power | 4 kW @1 MHz mW |
| Clock | 230 MHz |
Zest is the first SoC of the PULP group that features both Snitch and PULP clusters in a common architecture. IT also demonstrates the Fenrir peripheral system with UART, I2C, QSPI, Camera interface, DVSI event camera link as well as hyper bus, and a custom double data rate serial link. As a result of all these additions, it uses a rather large QFN88 package.
In total Zest has 8x RI5CY cores connected to 128 KiB TCDM memory, 4+1 Snitch cores in their own cluster with 128 KiB of private TCDM and an additional 256 KiB of shared memory for both clusters
There is an orange peel on the logo as a play on the name Zest