Paul Scheffler
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Designer for following chips
Publications related to the chips in the gallery
- Alessandro Ottaviano, Thomas Benz, Paul Scheffler, Luca Benini, "Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In", IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 10, pp. 3777-3781, Oct. 2023, DOI: 10.1109/TCSII.2023.3289186
- Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gurkaynak, Davide Rossi, Luca Benini, "Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET", In Proc. IEEE Symposium on VLSI Technology and Circuits 2024, Honolulu, HI, USA, 2024, pp. 1-2,, DOI: 10.1109/VLSITechnologyandCir46783.2024.10631529
- Thomas Benz, Paul Scheffler, Jannis Schoenleber, Luca Benini, "Iguana: An End-to-End Open-Source Linux-capable RISC-V SoC in 130nm CMOS", RISC-V Summit Europe 2023, Barcelona, Spain, June 5-9, 2023, DOI: https://doi.org/10.3929/ethz-b-000641980