|Dimensions||1250μm x 1250μm|
Thestral is a small test chip that contains our latest Snitch based compute clusters. Snitch cores are small 32bit RISC-V (RV32IMAF) cores that feature a tiny integer core, but a very powerful vectorizable FPU and extensions for stream processing.
The chip contains our next Snitcholution (Snitch evolution) with architectural improvements and extensive power gating infrastructure. Notable changes compared to the system in Baikonur are:
It features one governor core with an FPU (floating point unit) and an IPU (integer processing unit), a private TCDM (tightly coupled data memory), and a private instruction cache. The governor manages the SoC, including power management. The governor comes with a private FPU and DMA engine to provide additional computing capabilities for control tasks.
The primary compute is provided by the Snitch cluster consisting of 8 cores with FPU, a cluster control core with additional DMA capabilities, and 64 kByte TCDM.
This chip is meant to test some ideas with our new cluster-based systems, especially related to fine-grained power-gating. The fine-grained power gating will allow us to make silicon measurements on various power-saving modes. As a test vehicle, we had to sacrifice a bit the maximum operating frequency and on-chip memory.
Additional peripherals such as HyperBus, a serial link, USB, and I2C should provide enough infrastructure to operate the chip stand-alone. 24 kByte last level cache (LLC) are used to reduce expensive off-chip accesses to the HyperBus.
Thestral is the third chip in our Snitch based systems, following Billywig and Baikonur (which included 3x clusters and 1x governor). The naming continues a tradition we had with the Harry Potter universe. As described in the Harry Potter Fandom wiki Thestral can only be seen by people who've seen death.