Matheus Cavalcante

Designer for following chips

• Minpool (2021)
• Yun (2021)
• Hedwig (2022)
• Occamy (2022)
• Carfield (2023)

Publications related to the chips in the gallery

• Samuel Riedel, Matheus Cavalcante, Emmanouil Frouzakis, Domenic Wuethrich, Enis Mustafa, Arlind Billa, Luca Benini, "MinPool: A 16-core NUMA-L1 Memory RISC-V Processor Cluster for Always-on Image Processing in 65nm CMOS", 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Istanbul, Turkiye, 2023, pp. 1-4, DOI: 10.1109/ICECS58634.2023.10382925
  
  
• Matteo Perotti, Matheus Cavalcante, Alessandro Ottaviano, Jiantao Liu, Luca Benini, "Yun: An Open-Source, 64-Bit RISC-V-Based Vector Processor With Multi-Precision Integer and Floating-Point Support in 65-nm CMOS", IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 10, pp. 3732-3736, Oct. 2023, DOI: 10.1109/TCSII.2023.3292579
  
  
• Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gurkaynak, Davide Rossi, Luca Benini, "Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET", In Proc. IEEE Symposium on VLSI Technology and Circuits 2024, Honolulu, HI, USA, 2024, pp. 1-2,, DOI: 10.1109/VLSITechnologyandCir46783.2024.10631529