The IIS Chip Gallery
INVICOS (1988)
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by
| Application | Graphics |
| Technology | 2000 |
| Manufacturer | VLSI Tech |
| Type | Research |
| Package | DIP64 |
| Dimensions | 6400μm x 3200μm |
| Gates | 4 kGE |
| Voltage | 5 V |
| Clock | 50 MHz |
The aim of this chip was to develop a video scan converter system that enhances the quality of interlaced video images with PAL line and frame rates. The system stores,the even and odd video fields ata pixel clock rate of 14 MHz ainfor four field memories. The two most recently written field memories are read out alternatingly to compose a full non interlaced video frame. The readout pixel clock is independent of the write clock and may have any value up to 40 MHz.
The part of the field to be displayed can be programmed, and non-interlaced scanning rates exceeding 66Hz can be achieved producing a flickerfree display.
The name INVICOS stands for: Interlace-Noninterlace VIdeo COntroller with Scanfrequency increase"