The IIS Chip Gallery

Xavier (2019)

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by

Paul Scheffler, Dominik Bisang, Raphael Fischer, Luca Colagrande, Davide Schiavone, Francesco Conti, Alfio Di Mauro, Fabian Schuiki

Main Details

Application	Pulp
Technology	65
Manufacturer	UMC
Type	Semester Thesis
Package	QFN64
Dimensions	2626μm x 2626μm
Gates	3 MGE
Voltage	1.2 V
Power	20 mW @ 1.2 V, 100 MHz
Clock	250 MHz

Description

Xavier is an enhanced PULPissimo system, that has

• a RI5CY (RV32ICMF) core as its main processing element
• a uDMA system that is able to handle 8 SPI ports,
• Integrated filtering capabilities inside uDMA during data transfer for IIR, Template matching, and spike detection.
• a hardware accelerator for quantized neural networks (4b weights, 4b inputs), reaching 4.81 GMAC/s.
• a total of 512 kByte memory.

The HWPE based accelerator used in Xavier does not use the typical control FSM, but a small zero-riscy core (RV32-ICM) which can be programmed easily.

Xavier is a reference to Professor X from X-men. One of the application areas of the design with multiple SPI ports is to retrieve bio potentials (including EEG signals) in parallel from many independent signal sources. Cerebro was already taken by an earlier group of chips

.

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