Alfio Di Mauro
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Designer for following chips
Publications related to the chips in the gallery
- Davide Schiavone, Davide Rossi, Alfio Di Mauro, Frank K. Gurkaynak, Timothy Saxe, Mao Wang, Ket Chong Yap, Luca Benini, "Arnold: an eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End-Nodes", in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 4, pp. 677-690, April 2021 arXiv: 2006.14256 10.1109/TVLSI.2021.3058162
- Alfio Di Mauro, Francesco Conti, Davide Schiavone, Davide Rossi, Luca Benini, "Always-On 674uW @4GOP/s Error Resilient Binary Neural Networks With Aggressive SRAM Voltage Scaling on a 22-nm IoT End-Node", In IEEE Transactions on Circuits and Systems I: Regular Papers, Volume 67, Issue 11, November 2020, DOI: 10.1109/TCSI.2020.3012576
- Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Alfio Di Mauro, Luca Benini, Davide Rossi, "Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode", IEEE Transactions on Circuits and Systems I: Regular Papers, DOI: 10.1109/TCSI.2023.3254810
- Davide Rossi, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini, "Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode", in IEEE Journal of Solid-State Circuits, vol. 57, no. 1, pp. 127-139, Jan. 2022, DOI: 10.1109/JSSC.2021.3114881
- Moritz Scherer, Alfio Di Mauro, Georg Rutishauser, Tim Fischer, Luca Benini, "A 1036 TOp/s/W, 12.2 mW, 2.72 μJ/Inference All Digital TNN Accelerator in 22 nm FDX Technology for TinyML Applications", IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS 2022), DOI: 10.1109/COOLCHIPS54332.2022.9772668
- Francesco Conti, Davide Rossi, Gianna Paulin, Angelo Garofalo, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Vincent Huard, Olivier Montfort, Lionel Jure, N. Exibart, Pascal Gouedo, Mathieu Louvat, E. Botte, Luca Benini, "A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing", International Solid-State Circuits Conference (ISSCC 2023)
- Arpan Prasad, Moritz Scherer, Davide Rossi, Alfio Di Mauro, Manuel Eggimann, Jorge Tomas Gomez, Ziyun Li, Syed Shakib Sarwar, Zhao Wang, Barbara De Salvo, Luca Benini, "Siracusa: A Low-Power On-Sensor RISC-V SoC for Extended Reality Visual Processing in 16nm CMOS", IEEE 49th European Solid State Circuits Conference (ESSCIRC 2023), Lisbon, Portugal, 2023, pp. 217-220, DOI: 10.1109/ESSCIRC59616.2023.10268718