Alfio Di Mauro
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Designer for following chips
Publications related to the chips in the gallery
- Antonio Pullini, Davide Rossi, Igor Loi, Alfio Di Mauro, Luca Benini, "Mr.Wolf: A 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for IoT Edge Processing", In Proc. European Solid State Circuits Conference (ESSCIRC) 2018, 3-6 Sep 2018, Dresden, DOI: 10.1109/ESSCIRC.2018.8494247
- Davide Schiavone, Davide Rossi, Alfio Di Mauro, Frank K. Gurkaynak, Timothy Saxe, Mao Wang, Ket Chong Yap, Luca Benini, "Arnold: an eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End-Nodes", arXiv: 2006.14256
- Alfio Di Mauro, Francesco Conti, Davide Schiavone, Davide Rossi, Luca Benini, "Hyperdrive: A Systolically Scalable Binary-Weight CNN Inference Engine for mW IoT End-Nodes Always-On 674uW @4GOP/s Error Resilient Binary Neural Networks With Aggressive SRAM Voltage Scaling on a 22-nm IoT End-Node", In IEEE Transactions on Circuits and Systems I: Regular Papers, Volume 67, Issue 11, November 2020, DOI: 10.1109/TCSI.2020.3012576
- Hayate Okuhara, Ahmed Elnaqib, Davide Rossi, Alfio Di Mauro, Philipp Mayer, Pierpaolo Plestri, Luca Benini, "An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes", IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, 2020, pp. 1-5, DOI: 10.1109/ISCAS45731.2020.9181081
- Angelo Garofalo, Gianmarco Ottavi, Alfio Di Mauro, Francesco Conti, Guiseppe Tagliavini, Luca Benini, Davide Rossi, "A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode", IEEE 47th European Solid State Circuits Conference (ESSCIRC 2021), DOI: 10.1109/ESSCIRC53450.2021.9567767
- Davide Rossi, Francesco Conti, Manuel Eggimann, Stefan Mach, Alfio Di Mauro, Marco Guermandi, Giuseppe Tagliavini, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini, "A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7uW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode", In Proc. IEEE International Solid- State Circuits Conference (ISSCC) 2021, San Francisco, CA, USA, 2021, pp. 60-62, DOI: 10.1109/ISSCC42613.2021.9365939
- Moritz Scherer, Alfio Di Mauro, Georg Rutishauser Tim Fischer, Luca Benini, "A 1036 TOp/s/W, 12.2 mW, 2.72 μJ/Inference All Digital TNN Accelerator in 22 nm FDX Technology for TinyML Applications", IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS 2022), DOI: 10.1109/COOLCHIPS54332.2022.9772668
- Francesco Conti, Davide Rossi, Gianna Paulin, Angelo Garofalo, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Vincent Huard, Olivier Montfort, Lionel Jure, N. Exibart, Pascal Gouedo, Mathieu Louvat, E. Botte, Luca Benini, "A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing", International Solid-State Circuits Conference (ISSCC 2023)