Additional pictures below, click to see larger versions
|Dimensions||4950μm x 3780μm|
|Clock||420 (typical) MHz|
Marsellus is an all-digital heterogeneous SoC for AI-IoT end-nodes fabricated in GlobalFoundries 22nm FDX that combines
- A general-purpose cluster of 16 RISC-V digital signal processing cores attuned for the execution of a diverse range of workloads exploiting 4-bit and 2-bit arithmetic extensions (XpulpNN), with fused MAC&LOAD operations and floating-point support;
- A 2-8bit Reconfigurable Binary Engine (RBE) to accelerate 3x3 and 1x1 (pointwise) convolutions in DNNs;
- A set of On-Chip Monitoring (OCM) blocks connected to an Adaptive Body Biasing (ABB) generator and a hardware control loop, enabling on-the-fly adaptation of transistor threshold voltages.
Marsellus combines state-of-the-art parallel and heterogeneous acceleration with aggressive performance and voltage scalability thanks to ABB, leading to overall performance and efficiency gains of 3 orders of magnitude
Marsellus is a co-operation between ETH Zurich and Dolphin Design and includes a PULPopen instantiation as well as a low power PLL from the Energy Efficient Circuits and IoT Systems group here at IIS
The name of the chip continues our obsession with the Quentin Tarantino movie PULP fiction.
- Francesco Conti, Davide Rossi, Gianna Paulin, Angelo Garofalo, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Vincent Huard, Olivier Montfort, Lionel Jure, N. Exibart, Pascal Gouedo, Mathieu Louvat, E. Botte, Luca Benini, "A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing", International Solid-State Circuits Conference (ISSCC 2023)