Angelo Garofalo
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Designer for following chips
Publications related to the chips in the gallery
- Angelo Garofalo, Gianmarco Ottavi, Alfio Di Mauro, Francesco Conti, Guiseppe Tagliavini, Luca Benini, Davide Rossi, "A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode", IEEE 47th European Solid State Circuits Conference (ESSCIRC 2021), DOI: 10.1109/ESSCIRC53450.2021.9567767
- Angelo Garofalo, Matteo Perotti, Luca Valente, Yvan Tortorella, Alessandro Nadalini, Lica Benini, Davide Rossi, Francesco Conti, "DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training", IEEE Open Journal of the Solid-State Circuits Society, vol. 2, pp. 231-243, 2022, DOI: 10.1109/OJSSCS.2022.3210082
- Francesco Conti, Davide Rossi, Gianna Paulin, Angelo Garofalo, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Vincent Huard, Olivier Montfort, Lionel Jure, N. Exibart, Pascal Gouedo, Mathieu Louvat, E. Botte, Luca Benini, "A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing", International Solid-State Circuits Conference (ISSCC 2023)