Giuseppe Tagliavini
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Designer for following chips
Publications related to the chips in the gallery
- Antonio Pullini, Davide Rossi, Igor Loi, Giuseppe Tagliavini, Luca Benini, "Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing", In IEEE Journal of Solid-State Circuits, vol. 54, no. 7, pp. 1970-1981, July 2019, DOI: 10.1109/JSSC.2019.2912307
- Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Alfio Di Mauro, Luca Benini, Davide Rossi, "Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode", IEEE Transactions on Circuits and Systems I: Regular Papers, DOI: 10.1109/TCSI.2023.3254810
- Davide Rossi, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini, "Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode", in IEEE Journal of Solid-State Circuits, vol. 57, no. 1, pp. 127-139, Jan. 2022, DOI: 10.1109/JSSC.2021.3114881