The IIS Chip Gallery
Minpool (2021)
Additional pictures below, click to see larger versions
by
| Application | Pulp |
| Technology | 65 |
| Manufacturer | TSMC |
| Type | Research |
| Package | QFN56 |
| Dimensions | 2400μm x 2400μm |
| Gates | 2500 kGE |
| Voltage | 1.2 V |
| Power | 4 kW @1 MHz mW |
| Clock | 200 MHz |
Minpool is based on the Mempool design, MemPool is one of the projects of the PULP platform with the aim of placing a high number of cores in one chip. This is done with a special interconnect through which all cores can access the scratchpad memory of any other core. Minpool is a slightly scaled down version with 16 cores.
MinPool is a manycore computer architecture with the purpose of incorporating a high number of CPU cores on a chip die. One of the main issues with scaling multicore clusters to high core counts is the intercore latency. MinPool demonstrates an approach to scale up the L1-interconnect, while ensuring that the average memory access latency stays below 6 cycles. The CPU cores used in MinPool are RV32IMA Snitch cores, highly flexible, low energy, general-purpose CPU cores. They are configured to use the XPULPIMG extension.
In total Minpool has a modest 64KiB scratchpad memory, 8KiB of instruction cache and 64 KiB of L2 memory and is able to run at 200 MHz.
The internal name of the project is also Pinwheel, and the logo shows such a stylized pinwheel.