Frank K. Gurkaynak

Information

I am the director of the Microelectronics Design Center and a senior scientist at the Integrated Systems Laboratory of ETH Zurich. I was born in Istanbul, obtained my BSc. and M.Sc. degrees from Electrical and Electronical Engineering Department of the Istanbul Technical University and my Ph.D. from Integrated Systems Laboratory of ETH Zurich.

Links

• Personal home page
• IIS Page

Designer for following chips

• 2d_dct (2001)
• Pic16c5x (2002)
• Riddler (2002)
• Serpent (2002)
• Fastcore (2003)
• Roro (2003)
• Shirkhan (2003)
• Stereopsis (2003)
• Transparent_ide (2003)
• Ares (2004)
• Cpex4 (2004)
• Acacia (2005)
• Havannaclub (2005)
• Panacea (2005)
• Sherlock (2006)
• Squirrel (2006)
• Watson (2006)
• Pipenet (2007)
• Dicle (2009)
• Sbrinz (2009)
• Esper (2010)
• Pixcel (2010)
• Chipit (2011)
• Dynamite (2011)
• Jones (2011)
• Shabziger (2011)
• Troll3d (2011)
• Vesper (2011)
• Dauerwelle (2012)
• Gemini (2012)
• Madmax (2012)
• Polygamy (2012)
• Cronorx (2013)
• Or10n (2013)
• Pulp (2013)
• Sir10us (2013)
• Artemis (2014)
• Diana (2014)
• Hecate (2014)
• Pulpv2 (2014)
• Selene (2014)
• Diego (2015)
• Honey_bunny (2015)
• Manny (2015)
• Mia_wallace (2015)
• Sid (2015)
• Hedwig (2022)
• Occamy (2022)
• Carfield (2023)
• Iguana (2023)

Publications related to the chips in the gallery

• Adrian Lutz, Juerg Treichler, Frank K. Gurkaynak, Hubert Kaeslin, Gerard Basler, Andres Erni, Stephan Reichmuth, Pieter Rommens, Stephan Oetiker, Wolfgang Fichtner, "2 Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A comparative analysis", Lecture Notes in Computer Science vol 2533, CHES 2002, DOI: 10.1007/3-540-36400-5_12
  
  
• Frank K. Gurkaynak, Andreas Burg, Dominique Gasser, Franco Hug, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner, "A 2Gb/s Balanced AES Crypto-Chip Implementation", 14th ACM Great Lakes VLSI Symposium, GLSVLSI 2004, DOI: 10.1145/988952.988963
  
  
• Stephan Oetiker, Thomas Villiger, Frank K. Gurkaynak, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, "High resolution Clock Generators for Globally-Asynchronous Locally Synchronous Designs", In handouts of Second Asynchronous Circuit Design Workshop (ACiD 2002), Munich
  
  
• Thomas Villiger, Hubert Kaeslin, Frank K. Gurkaynak, Stephan Oetiker, Wolfgang Fichtner, "Self-Timed Ring for Globally-Asynchronous Locally Synchronous Systems", In proc. of 9th International Symposium on Asynchronous Circuits and Systems, ASYNC 2003, Vancouver, DOI: 10.1109/ASYNC.2003.1199174
  
  
• Michael Kuhn, Stephan Moser, Oliver Isler, Frank K. Gurkaynak, Andreas Burg, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner, "Efficient ASIC implementation of a real-time depth mapping stereo vision system", IEEE Midwestern Symposium on Circuits and Systems MWSCAS 2003
  
  
• Norbert Pramstaller, Frank K. Gurkaynak, Simon Haene, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, "Towards an AES crypto-chip resistant to differential power analysis", Proceeding of the 30th European Solid-State Circuits Conference, 2004. ESSCIRC 2004. Page(s): 307 - 310, DOI: 10.1109/ESSCIR.2004.1356679
  
  
• Frank K. Gurkaynak, Stephan Oetiker, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner, "Improving DPA security by using globally-asynchronous locally-synchronous systems", Proceedings of the 31st European Solid-State Circuits Conference, ESSCIRC 2005, Page(s): 407 - 410, DOI: 10.1109/ESSCIR.2005.1541646
  
  
• Frank K. Gurkaynak, Peter Luethi, Nico Bernold, Rene Blattmann, Victoria Goode, Marcel Marghitola, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, "Hardware Evaluation of eSTREAM Candidates: Achterbahn, Grain, Mickey, Mosquito, Sfinks, Trivium, Vest, ZK-Crypt", Proc. Of the SASC 2006 Workshop - Stream Ciphers Revisited, Leuven Belgium
  
  
• Luca Henzen, Pietro Gendotti, Patrice Guillet, Enrico Pargaetzi, Martin Zoller, Frank K. Gurkaynak, "Developing a Hardware Evaluation Method for SHA-3 Candidates", In Proc. Cryptographic Hardware for Embedded Systems Workshop (CHES) 2010, LNCS vol 6225/2010, page(s): 248-263, DOI: 10.1007/978-3-642-15031-9_17
  
  
• Michael Muehlberghuber, Frank K. Gurkaynak, Thomas Korak, Philipp Dunst, Michael Hutter, "Red team vs. blue team hardware trojan analysis: detection of a hardware trojan on an actual ASIC", Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy (HASP'13), DOI: 10.1145/2487726.2487727
  
  
• Pierre Greisen, Richard Emler, Michael Schaffner, Simon Heinzle, Frank K. Gurkaynak, "A general-transformation EWA view rendering engine for 1080p video in 130 nm CMOS", IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC 2012) pp:105-110, DOI: 10.1109/VLSI-SoC.2012.6379014
  
  
• Pierre Greisen, Michael Schaffner, Danny Luu, Val Mikos, Simon Heinzle, Frank K. Gurkaynak, Aljoscha Smolic, "Spatially-Varying Image Warping: Evaluations and VLSI Implementations", Chapter in, VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, DOI: 10.1007/978-3-642-45073-0_4
  
  
• Christoph Nagl, Michael Muehlberghuber, Frank K. Gurkaynak, "Evaluation of the back-end design overhead for ASIC implementations of large-operand multipliers targeting resource-constrained environments", 22nd Austrian Workshop on Microelectronics (Austrochip), 9 Oct. 2014, Graz, Austria, DOI: 10.1109/Austrochip.2014.6946314
  
  
• Michael Schaffner, Pierre Greisen, Simon Heinzle, Frank K. Gurkaynak, Hubert Kaeslin, Aljoscha Smolic, "MADmax: A 1080p stereo-to-multiview rendering ASIC in 65 nm CMOS based on image domain warping", Proceedings of the ESSCIRC (ESSCIRC), 2013, pp-61-64, DOI: 10.1109/ESSCIRC.2013.6649072
  
  
• Michael Schaffner, Lukas Cavigelli, Pascal Alexander Hager, Pierre Greisen, Frank K. Gurkaynak, Hubert Kaeslin, "A real-time 720p feature extraction core based on Semantic Kernels Binarized", IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC 2013), pp 27-32, DOI: 10.1109/VLSI-SoC.2013.6673240
  
  
• Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank K. Gurkaynak, Andrea Bartolini, Philippe Flatresse, Luca Benini, "A 60 GOPS/W, -1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology", Journal of Solid-State Electronics, Volume 117, March 2016, Pages 170-184, DOI: 10.1016/j.sse.2015.11.015
  
  
• Michael Gautschi, Michael Schaffner, Frank K. Gurkaynak, Luca Benini, "An Extended Shared Logarithmic Unit for Nonlinear Function Kernel Acceleration in a 65-nm CMOS Multicore Cluster", IEEE Journal of Solid-State Circuits, Volume: 52, Issue: 1, Jan. 2017, pp 98-112, DOI: 10.1109/JSSC.2016.2626272
  
  
• Vincent Camus, Jeremy Schlachter, Christian Enz, Frank K. Gurkaynak, Michael Gautschi, "Approximate 32-bit floating-point unit design with 53% power-area product reduction", ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, 2016, pp. 465-468., DOI: 10.1109/ESSCIRC.2016.7598342
  
  
• Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank K. Gurkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro-Panades, Edith Beigne, Fabien Clermidy, Philippe Flatresse, Luca Benini, "Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster", IEEE Micro, vol. 37, no. 5, pp. 20-31, DOI: 10.1109/MM.2017.3711645
  
  
• Michael Gautschi, Michael Schaffner, Frank K. Gurkaynak, Luca Benini, "A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster", 2016 IEEE International Solid-State Circuits Conference (ISSCC), pp 82 - 83, DOI: 10.1109/ISSCC.2016.7417917
  
  
• Francesco Conti, Robert Schilling, Davide Schiavone, Antonio Pullini, Davide Rossi, Frank K. Gurkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haougou, Stefan Mangard, Luca Benini, "An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics", IEEE Transactions on Circuits and Systems I: Regular Papers, Vol: 64, Issue: 9, Sept. 2017, pp 2481 - 2494, DOI: 10.1109/TCSI.2017.2698019
  
  
• Michael Schaffner, Michael Gautschi, Frank K. Gurkaynak, Luca Benini, "Accuracy and Performance Trade-offs of Logarithmic Number Units in Multi-Core Clusters", 23rd IEEE Symposium on Computer Arithmetic (ARITH 2016), Santa Clara USA, DOI: 10.1109/ARITH.2016.10
  
  
• Florian Glaser, Stefan Mach, Abbas Rahimi, Frank K. Gurkaynak, Qiuting Huang, Luca Benini, "An 826 MOPS, 210uW/MHz Unum ALU in 65 nm", In Proc. 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 27-30 May 2018, Florence, Italy, pp 1-5, DOI: 10.1109/ISCAS.2018.8351546
  
  
• Davide Schiavone, Davide Rossi, Alfio Di Mauro, Frank K. Gurkaynak, Timothy Saxe, Mao Wang, Ket Chong Yap, Luca Benini, "Arnold: an eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End-Nodes", in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 4, pp. 677-690, April 2021 arXiv: 2006.14256 10.1109/TVLSI.2021.3058162
  
  
• Odem Harel, Emanuel Nieto Casarrubias, Manuel Eggimann, Frank K. Gurkaynak, Luca Benini, Adam Teman, Robert Gitermann, Andreas Burg, "64-kB 65-nm GC-eDRAM With Half-Select Support and Parallel Refresh Technique", in IEEE Solid-State Circuits Letters, vol. 5, pp. 170-173, 2022, DOI: 10.1109/LSSC.2022.3182531
  
  
• Thomas Benz, Luca Bertaccini, Florian Zaruba, Fabian Schuiki, Frank K. Gurkaynak, Luca Benini, "A 10-core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing over a Wide Voltage and Temperature Range", In Proc. IEEE 47th European Solid State Circuits Conference (ESSCIRC), Grenoble, France, 2021, pp. 263-266, DOI: 10.1109/ESSCIRC53450.2021.9567755