Hubert Kaeslin

Designer for following chips

• Fourbit_multiplier (1986)
• Parallel_multiplier2 (1986)
• Parallel_multiplier3 (1986)
• Viterbi (1987)
• Autobus (1990)
• Lpc (1991)
• Fiforam (1992)
• Arithmetic_coder (1993)
• Safer (1995)
• Wirthlinx (1995)
• Usb (1998)
• Riddler (2002)

Publications related to the chips in the gallery

• Marc Biver, Hubert Kaeslin, Carlo Tommasini, "Architectural design and realization of a single-chip Viterbi decoder", Integration, the VLSI Journal, Volume 8, Issue 1, October 1989, Pages 3-16, DOI: 10.1016/0167-9260(89)90069-2
  
  
• Heinz Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, Xuejia Lai, "VLSI implementation of a new block cipher", In Proceedings IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD '91, 14-16 Oct 1991page(s): 510-513, DOI: 10.1109/ICCD.1991.139960
  
  
• Reto Zimmermann, Andreas Curiger, Heinz Bonnenberg, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, "A 177 Mb/s VLSI implementation of the International Data Encryption Algorithm", IEEE Journal of Solid-State Circuits, Mar 1994, Vol: 29, Issue:3, page(s): 303 - 307, DOI: 10.1109/4.278352
  
  
• Jens Muttersbach, Thomas Villiger, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, "Globally-asynchronous locally-synchronous architectures to simplify the design of on-chip systems", IN proc. Twelfth Annual IEEE International ASIC/SOC Conference, Sep 1999, page: 317-321, DOI: 10.1109/ASIC.1999.806526
  
  
• Thomas Roewer, Manfred Stadler, Markus Thalmann, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner, "Intellectual property module of a highly parametrizable embedded stack processor", In Proceedings, Twelfth Annual IEEE International ASIC/SOC Conference, 1999, page(s): 399 - 403, DOI: 10.1109/ASIC.1999.806542
  
  
• Peter Luethi, Thomas Roewer, Manfred Stadler, Daniel Forrer, Stefan Moscibroda, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner, "A parametrizable hybrid stack-register processor as soft intellectual property module", 13th Annual IEEE International ASIC/SOC Conference, 2000, page(s): 87 - 91, DOI: 10.1109/ASIC.2000.880681
  
  
• Adrian Lutz, Juerg Treichler, Frank K. Gurkaynak, Hubert Kaeslin, Gerard Basler, Andres Erni, Stephan Reichmuth, Pieter Rommens, Stephan Oetiker, Wolfgang Fichtner, "2 Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A comparative analysis", Lecture Notes in Computer Science vol 2533, CHES 2002, DOI: 10.1007/3-540-36400-5_12
  
  
• Frank K. Gurkaynak, Andreas Burg, Dominique Gasser, Franco Hug, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner, "A 2Gb/s Balanced AES Crypto-Chip Implementation", 14th ACM Great Lakes VLSI Symposium, GLSVLSI 2004, DOI: 10.1145/988952.988963
  
  
• Stephan Oetiker, Thomas Villiger, Frank K. Gurkaynak, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, "High resolution Clock Generators for Globally-Asynchronous Locally Synchronous Designs", In handouts of Second Asynchronous Circuit Design Workshop (ACiD 2002), Munich
  
  
• Thomas Villiger, Hubert Kaeslin, Frank K. Gurkaynak, Stephan Oetiker, Wolfgang Fichtner, "Self-Timed Ring for Globally-Asynchronous Locally Synchronous Systems", In proc. of 9th International Symposium on Asynchronous Circuits and Systems, ASYNC 2003, Vancouver, DOI: 10.1109/ASYNC.2003.1199174
  
  
• Michael Kuhn, Stephan Moser, Oliver Isler, Frank K. Gurkaynak, Andreas Burg, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner, "Efficient ASIC implementation of a real-time depth mapping stereo vision system", IEEE Midwestern Symposium on Circuits and Systems MWSCAS 2003
  
  
• Flavio Carbognani, Felix Buergin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner, "Two-Phase Resonant Clocking for Ultra-Low-Power Hearing Aid Applications", In Proc. Design, Automation and Test in Europe, 2006. DATE '06., DOI: 10.1109/DATE.2006.243985
  
  
• Norbert Pramstaller, Frank K. Gurkaynak, Simon Haene, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, "Towards an AES crypto-chip resistant to differential power analysis", Proceeding of the 30th European Solid-State Circuits Conference, 2004. ESSCIRC 2004. Page(s): 307 - 310, DOI: 10.1109/ESSCIR.2004.1356679
  
  
• Flavio Carbognani, Felix Buergin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner, "Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications", In. Proc. International Workshop on Power and Timing Modelling, Optimization and Simulation PATMOS 2005, DOI: 10.1007/11556930_46
  
  
• Frank K. Gurkaynak, Stephan Oetiker, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner, "Improving DPA security by using globally-asynchronous locally-synchronous systems", Proceedings of the 31st European Solid-State Circuits Conference, ESSCIRC 2005, Page(s): 407 - 410, DOI: 10.1109/ESSCIR.2005.1541646
  
  
• Flavio Carbognani, Felix Buergin, Luca Henzen, Herbert Koch, Hovig Magdassian, Christoph Pedretti, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, "A 0.67-mm2 45uW DSP VLSI implementation of an adaptive directional microphone for hearing aids", Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005., DOI: 10.1109/ECCTD.2005.1523080
  
  
• Tim Weyrich, Simon Heinzle, Timo Aila, Daniel B. Fasnacht, Stephan Oetiker, Mario Botsch, Cyril Flaig, Simon Mall, Kaspar Rohrer, Norbert Felber, Hubert Kaeslin, Markus Gross, "A hardware architecture for surface splatting", ACM Transactions on Graphics (TOG) - Proceedings of ACM SIGGRAPH 2007, Volume 26 Issue 3, July 2007, DOI: 10.1145/1276377.1276490
  
  
• Flavio Carbognani, Felix Buergin, Daniel Kraehenbuehl, Frank Zuercher, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner, "Low-power constant-coefficient FIR filtering in a hearing aid application", 8th International Conference on Solid-State and Integrated Circuit Technology, ICSICT '06, Page(s): 1637 - 1639, DOI: 10.1109/ICSICT.2006.306357
  
  
• Felix Buergin, Flavio Carbognani, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, "29% Power Saving through Semi-Custom Standard Cell Re-Design in a Front-End for Hearing Aids", 49th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS '06, Page(s): 610 - 614, DOI: 10.1109/MWSCAS.2006.382137
  
  
• Flavio Carbognani, Felix Buergin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner, "Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, July 2008, Vol: 16 , Issue:7, page(s): 830 - 836, DOI: 10.1109/TVLSI.2008.2000457
  
  
• Flavio Carbognani, Simon Haene, Manuel Arrigo, Claudio Pagnamenta, Felix Buergin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner, "A 0.25um 0.92 mW per Mb/s Viterbi decoder featuring resonant clocking for ultra-low-power 54 Mb/s WLAN communication", IEEE Custom Integrated Circuits Conference, CICC '07, Page(s): 451 - 454, DOI: 10.1109/CICC.2007.4405771
  
  
• Frank K. Gurkaynak, Peter Luethi, Nico Bernold, Rene Blattmann, Victoria Goode, Marcel Marghitola, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, "Hardware Evaluation of eSTREAM Candidates: Achterbahn, Grain, Mickey, Mosquito, Sfinks, Trivium, Vest, ZK-Crypt", Proc. Of the SASC 2006 Workshop - Stream Ciphers Revisited, Leuven Belgium
  
  
• Peter Luethi, Christoph Studer, Sebastian Duetsch, Eugen Zgraggen, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, "Gram-Schmidt-based QR decomposition for MIMO detection: VLSI implementation and comparison", IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2008, Page(s): 830 - 833, DOI: 10.1109/APCCAS.2008.4746151
  
  
• Pierre Greisen, Michael Schaffner, Simon Heinzle, Marian Runo, Aljoscha Smolic, Andreas Burg, Hubert Kaeslin, Markus Gross, "Analysis and VLSI Implementation of EWA Rendering for Real-Time HD Video Applications", IEEE Transactions on Circuits and Systems for Video Technology, vol:22, Issue:11, pp:1577-1589, DOI: 10.1109/TCSVT.2012.2201671
  
  
• Patrick Maechler, Christoph Studer, David Bellasi, Arian Maleki, Andreas Burg, Norbert Felber, Hubert Kaeslin, Richard Baraniuk, "VLSI Design of Approximate Message Passing for Signal Restoration and Compressive Sensing", IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol:2, issue:3, pp 579-590, DOI: 10.1109/JETCAS.2012.2214636
  
  
• Michael Schaffner, Pierre Greisen, Simon Heinzle, Frank K. Gurkaynak, Hubert Kaeslin, Aljoscha Smolic, "MADmax: A 1080p stereo-to-multiview rendering ASIC in 65 nm CMOS based on image domain warping", Proceedings of the ESSCIRC (ESSCIRC), 2013, pp-61-64, DOI: 10.1109/ESSCIRC.2013.6649072
  
  
• Michael Schaffner, Lukas Cavigelli, Pascal Alexander Hager, Pierre Greisen, Frank K. Gurkaynak, Hubert Kaeslin, "A real-time 720p feature extraction core based on Semantic Kernels Binarized", IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC 2013), pp 27-32, DOI: 10.1109/VLSI-SoC.2013.6673240
  
  
• Michael Gautschi, Michael Muehlberghuber, Andreas Traber, Sven Stucki, Matthias Baer, Renzo Andri, Beat Muheim, Luca Benini, Hubert Kaeslin, "SIR10US: A tightly coupled elliptic-curve cryptography co-processor for the OpenRISC", 2014 IEEE 25th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 18-20 June 2014, Zurich, pp 25-29, DOI: 10.1109/ASAP.2014.6868626