Pierre Greisen
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Publications related to the chips in the gallery
- Andreas Burg, Simon Haene, Moritz Borgmann, Daniel Baum, Thomas Thaler, Flavio Carbognani, Stefan Zwicky, Luis Barbero, Christian Senning, Pierre Greisen, Thomas Peter, Claudio Foelmli, Pedro Tejera, Ulrich Schuster, Andy Staudacher, "A 4-stream 802.11n baseband transceiver in 0.13um CMOS", Symposium on VLSI Circuits, 16-18 June 2009, page(s): 282 - 283, Kyoto, Japan
- Patrick Maechler, Pierre Greisen, Norbert Felber, Andreas Burg, "Matching pursuit: Evaluation and implementatio for LTE channel estimation", IEEE International Symposium on Circuits and Systems (ISCAS 2010), pp 589-592, DOI: 10.1109/ISCAS.2010.5537528
- Pierre Greisen, Michael Schaffner, Simon Heinzle, Marian Runo, Aljoscha Smolic, Andreas Burg, Hubert Kaeslin, Markus Gross, "Analysis and VLSI Implementation of EWA Rendering for Real-Time HD Video Applications", IEEE Transactions on Circuits and Systems for Video Technology, vol:22, Issue:11, pp:1577-1589, DOI: 10.1109/TCSVT.2012.2201671
- Pierre Greisen, Richard Emler, Michael Schaffner, Simon Heinzle, Frank K. Gurkaynak, "A general-transformation EWA view rendering engine for 1080p video in 130 nm CMOS", IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC 2012) pp:105-110, DOI: 10.1109/VLSI-SoC.2012.6379014
- Pierre Greisen, Michael Schaffner, Danny Luu, Val Mikos, Simon Heinzle, Frank K. Gurkaynak, Aljoscha Smolic, "Spatially-Varying Image Warping: Evaluations and VLSI Implementations", Chapter in, VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, DOI: 10.1007/978-3-642-45073-0_4
- Michael Schaffner, Pierre Greisen, Simon Heinzle, Frank K. Gurkaynak, Hubert Kaeslin, Aljoscha Smolic, "MADmax: A 1080p stereo-to-multiview rendering ASIC in 65 nm CMOS based on image domain warping", Proceedings of the ESSCIRC (ESSCIRC), 2013, pp-61-64, DOI: 10.1109/ESSCIRC.2013.6649072
- Michael Schaffner, Lukas Cavigelli, Pascal Alexander Hager, Pierre Greisen, Frank K. Gurkaynak, Hubert Kaeslin, "A real-time 720p feature extraction core based on Semantic Kernels Binarized", IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC 2013), pp 27-32, DOI: 10.1109/VLSI-SoC.2013.6673240