The IIS Chip Gallery

clsn601p (2008)

by

Andreas Burg, Simon Haene, Christian Senning, Moritz Borgmann, Daniel Baum, Thomas Thaler, Flavio Carbognani, Stefan Zwicky, Luis Barbero, Pierre Greisen, Claudio Foelmli, Ulrich Schuster, Pedro Tejera, Andy Staudacher

Main Details

Application	Communication
Technology	130
Manufacturer	UMC
Type	Research Project
Package	PGA208
Dimensions	5000μm x 5000μm
Gates	1200 kGE
Voltage	1.2 V
Clock	80-320 MHz

Description

The IEEE 802.11n wireless LAN standard relies on multiple-input multiple-output (MIMO) technology with up to 4 spatial streams to provide high data rates across a wide range with wire-like quality of service. Unfortunately, the circuit complexity of a corresponding MIMO baseband transceiver grows rapidly with the number of spatial streams. Hence, current commercial implementations of IEEE 802.11n support only up to 2 streams with 2 or 3 antennas and are limited to data rates of 300 Mbps.

In this research project, a fully IEEE 802.11n compliant MIMO-OFDM baseband transceiver ASIC was developed. The circuit is the worldwide first implementation of IEEE 802.11n that supports up to 4 spatial streams with a bandwidth of 40 MHz to achieve up to 600 Mbps throughput. The innovative architecture of the industrial-grade design was tailored to efficiently handle the complexity of modern communication standards and is well suited as a basis for a variety of future research projects.

The initial implementation was realized in a 130 nm CMOS technology. The manufactured prototype ASIC employs a soft-output MMSE receiver for MIMO detection. Optimizations on the algorithm and architectural level lead to a core area of the 4-stream transceiver that is almost on par with the area of commercial state-of-the-art 2-stream IEEE 802.11n transceiver ASIC implementations.

The chip features:

• 49 on-chip RAMs (!) for a total of more than 500'000 bits
• 910'000 standard cells
• more than ten million transistors (!)
• 370 MHz clock
• 1 phase-locked loop
• 19-level clock tree of roughly 1'300 buffers (!)
• 130 nm single-poly 8-metal CMOS
• 14 mm2 core area
• 268 pins
• 27 m of interconnect

Related Publication

• Andreas Burg, Simon Haene, Moritz Borgmann, Daniel Baum, Thomas Thaler, Flavio Carbognani, Stefan Zwicky, Luis Barbero, Christian Senning, Pierre Greisen, Thomas Peter, Claudio Foelmli, Pedro Tejera, Ulrich Schuster, Andy Staudacher, "A 4-stream 802.11n baseband transceiver in 0.13um CMOS", Symposium on VLSI Circuits, 16-18 June 2009, page(s): 282 - 283, Kyoto, Japan