The IIS Chip Gallery

Sandstorm (2012)

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by

Lukas Cavigelli, Pascal Alexander Hager, Oliver With, Michael Schaffner, Pierre Greisen

Main Details

Application	Graphics
Technology	180
Manufacturer	UMC
Type	Semester Thesis
Package	QFP120
Dimensions	3240μm x 1525μm
Gates	250 kGE
Voltage	1.8 V
Power	146 mW, 100MHz 1.8V
Clock	100 MHz

Description

This ASIC realizes a Semantic Kernals Binarized (SKB) method for finding correspondence points in a stereo video stream. The system has beend esigned to work on two Application-Specific Integrated Circuit (ASIC) embedded in an Field Programmable Gate Array (FPGA) environment. The key parts of the algorithm, interest points detection and their description, are carried out on one ASIC per channel. As it is a memory intensive algorithm, the FPGA feeds the ASIC with the required data stored in its internal memory. Also done on the FPGA is the matching of the descriptors, reception and retransmission of the Digital Video Interface (DVI) signals as well as overlaying images with the calculated disparity map.

The paper related to this chip won the best paper award at the International Conference on Very Large Scale Integration VLSI-SoC-2013

Related Publication

• Michael Schaffner, Lukas Cavigelli, Pascal Alexander Hager, Pierre Greisen, Frank K. Gurkaynak, Hubert Kaeslin, "A real-time 720p feature extraction core based on Semantic Kernels Binarized", IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC 2013), pp 27-32, DOI: 10.1109/VLSI-SoC.2013.6673240