Michael Gautschi
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Designer for following chips
Publications related to the chips in the gallery
- Sandro Belfanti, Christoph Roth, Michael Gautschi, Christian Benkeser, Qiuting Huang, "A 1Gbps LTE-advanced turbo-decoder ASIC in 65nm CMOS", Symposium on VLSI Circuits (VLSIC), 2013, pp C284-C285
- Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank K. Gurkaynak, Andrea Bartolini, Philippe Flatresse, Luca Benini, "A 60 GOPS/W, -1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology", Journal of Solid-State Electronics, Volume 117, March 2016, Pages 170-184, DOI: 10.1016/j.sse.2015.11.015
- Michael Gautschi, Michael Muehlberghuber, Andreas Traber, Sven Stucki, Matthias Baer, Renzo Andri, Beat Muheim, Luca Benini, Hubert Kaeslin, "SIR10US: A tightly coupled elliptic-curve cryptography co-processor for the OpenRISC", 2014 IEEE 25th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 18-20 June 2014, Zurich, pp 25-29, DOI: 10.1109/ASAP.2014.6868626
- Michael Gautschi, Michael Schaffner, Frank K. Gurkaynak, Luca Benini, "An Extended Shared Logarithmic Unit for Nonlinear Function Kernel Acceleration in a 65-nm CMOS Multicore Cluster", IEEE Journal of Solid-State Circuits, Volume: 52, Issue: 1, Jan. 2017, pp 98-112, DOI: 10.1109/JSSC.2016.2626272
- Vincent Camus, Jeremy Schlachter, Christian Enz, Frank K. Gurkaynak, Michael Gautschi, "Approximate 32-bit floating-point unit design with 53% power-area product reduction", ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, 2016, pp. 465-468., DOI: 10.1109/ESSCIRC.2016.7598342
- Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank K. Gurkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro-Panades, Edith Beigne, Fabien Clermidy, Philippe Flatresse, Luca Benini, "Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster", IEEE Micro, vol. 37, no. 5, pp. 20-31, DOI: 10.1109/MM.2017.3711645
- Michael Gautschi, Michael Schaffner, Frank K. Gurkaynak, Luca Benini, "A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster", 2016 IEEE International Solid-State Circuits Conference (ISSCC), pp 82 - 83, DOI: 10.1109/ISSCC.2016.7417917
- Francesco Conti, Robert Schilling, Davide Schiavone, Antonio Pullini, Davide Rossi, Frank K. Gurkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haougou, Stefan Mangard, Luca Benini, "An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics", IEEE Transactions on Circuits and Systems I: Regular Papers, Vol: 64, Issue: 9, Sept. 2017, pp 2481 - 2494, DOI: 10.1109/TCSI.2017.2698019
- Antonio Pullini, Francesco Conti, Davide Rossi, Igor Loi, Michael Gautschi, Luca Benini, "A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision", IEEE Transactions on Circuits and Systems II: Express Briefs ( Volume: PP, Issue: 99 ), 2017, DOI: 10.1109/TCSII.2017.2652982
- Michael Schaffner, Michael Gautschi, Frank K. Gurkaynak, Luca Benini, "Accuracy and Performance Trade-offs of Logarithmic Number Units in Multi-Core Clusters", 23rd IEEE Symposium on Computer Arithmetic (ARITH 2016), Santa Clara USA, DOI: 10.1109/ARITH.2016.10