The IIS Chip Gallery
Honey_Bunny (2015)
Additional pictures below, click to see larger versions
by
| Application | Pulp |
| Technology | 28 |
| Manufacturer | GF |
| Type | Research |
| Package | QFN56 |
| Dimensions | 1500μm x 2000μm |
| Gates | 2 MGE |
| Voltage | 1.2 V |
| Power | 1 mW @1.2V 1MHz |
| Clock | 60 MHz |
Honey Bunny is the first PULP chip that uses RI5CY, our RISC-V implementation with compressed instructions. It has been designed to have sufficient memory (256kBytes) and interfaces to be used in a wide variety of practical applications.
Honey Bunny contains four RI5CY cores, 256 kBytes of L2 memory, 64 kBytes of TCDM as SRAMs and an additional 4 kBytes as standard cell based memories.
A new version of the FLL used in the Mia Wallace has been redesigned to be used in the Globalfoundries 28nm technology and is able to generate the desired operating frequency (0-666MHz) from a simple 32kHz crystal oscillator.
As can be imagined we are all fans of Pulp Fiction and this series of PULP chips will be named after characters from this movie. Honey Bunny (or shortly Honey) is this chip.