The IIS Chip Gallery

Pulpv2 (2014)

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by

Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank K. Gurkaynak, Luca Benini

Main Details

Application	Pulp
Technology	28
Manufacturer	STM
Type	Research
Package	QFN64
Dimensions	1650μm x 1650μm
Gates	1800 kGE
Voltage	1.0 V
Power	100 mW
Clock	1000 MHz

Description

Parallel Ultra Low power Processor (PULP) is a shared data memory, parallel processor architecture. This version differs from the previous Pulp v1 by the following points:

• Using the faster low-leakage (LVT) transistors
• Integrated FLL for generating the clock internally
• Standard cell based memories for low-voltage operation
• AXI busses for on-chip busses
• Master and Slave SPI interfaces allowing the chip to be used in real environments
This version of the chip was implemented using ST28 FDSOI technology and contains one cluster with 4 OpenRISC cores modified to have much higher IPC and a dedicated DMA controller. It has 64 kBytes of L2 memory, 40 kBytes of TCDM (out of which 8 Kbytes is SCM), and in total 4 kBytes of private SCM.

The chip has been designed in collaboration with University of Bologna, EPFL, CEA-LETI and ST Microelectronics Grenoble

Related Publication

• Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank K. Gurkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro-Panades, Edith Beigne, Fabien Clermidy, Philippe Flatresse, Luca Benini, "Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster", IEEE Micro, vol. 37, no. 5, pp. 20-31, DOI: 10.1109/MM.2017.3711645