The IIS Chip Gallery
Stereopsis (2003)
by
| Application | Graphics |
| Technology | 250 |
| Manufacturer | UMC |
| Type | Semester Thesis |
| Package | LCC84 |
| Dimensions | 2500μm x 2500μm |
| Gates | 90 kGE |
| Voltage | 2.5 V |
| Clock | 100 MHz |
Depth mapping by passive stereo vision is a method to extract spatial depth information for a scene from a parallel pair of horizontally displaced stereo images. The relative perspective shift of objects or image features is calculated into a distance value. Possible applications include collision detection for intelligent transportation systems as well as industrial automated production.
In this project a hardware-efficient architecture of a stereo vision module for fast dynamic applications was implemented. The design combines two well-known approaches to stereo matching. Hardware efficiency is achieved by storing only partial images on-chip, avoiding full-sized frame buffers. The output is made up of a disparity map for visualization or further digital processing. A low-latency dataflow-oriented structure makes it possible to process 256by192 pixel input streams with a rate in excess of 50 frames per second, amounting to more than 54 million pixel disparity measurements per second (for a 25pixel disparity range), or roughly 18GOPS. The design has been integrated in a 0.25 μm standard CMOS technology and occupies an area of less than 3mm2.