The IIS Chip Gallery
CPE (1995)
by
| Application | Processor |
| Technology | 1200 |
| Manufacturer | VLSI Tech |
| Type | Semester Thesis |
| Package | PGA84 |
| Dimensions | 4600μm x 4200μm |
| Gates | 8 kGE |
| Voltage | 5 V |
| Clock | 25 MHz |
A CORDIC (COordinate Rotation DIgital Computer) allows the rotation of vectors, either by a given angle (rotation mode) or onto the x-axis (vectoring mode). Thereby, the rotated vector as well as the rotation angle is calculated. Givens rotations can be computed by using several CORDICs. In this work, a CORDIC processor element (CPE) was developed on an ASIC. It contains two CORDIC units and can easily be concatenated to a systolic array, which allows the computation of entire QR-decompositions. For integration of a systolic array on an Multi-Chip Module (MCM), the CPE includes special circuit structures for hardware testing and correction purposes (hardware redundancy).
As an application for adaptive antennas, radar, and sonar systems, an antenna processor can be imple mented on an MCM using 40 CPEs, which performs recursive least-square minimization via orthogonal matrix triangularization.
Since unpackaged dies are required for integration on an MCM, dedicated test structures were implemented, allowing for a full fabrication test with only 10 pad probes.