The IIS Chip Gallery
Arnold (2018)
Additional pictures below, click to see larger versions
by
| Application | Pulp |
| Technology | 22 |
| Manufacturer | GF |
| Type | Research Project |
| Package | QFN64 |
| Dimensions | 3000μm x 3000μm |
| Gates | 1 |
| Voltage | 0.8 V |
| Power | not available yet mW |
| Clock | 330 MHz |
This chip combines our successful PULPissimo line of microcontrollers with an eFPGA from Quicklogic corporation. The eFPGA can be programmed through the RI5CY core in the PULPissimo using memory mapped read/write operations. The eFPGA has also an extra APB bus interface which allows it to be accessed as a standard peripheral, but more interestingly it also has 4 TCDM access ports allowing it to access the same 512kByte on chip memory that the processor can access directly.
The chip also features a rich set of peripherals and a uDMA system that is able to copy data to and from the peripherals. There is an experimental mode in the chip that would allow the eFPGA to be connected in these uDMA transfers.
Communication between the RI5CY core and the eFPGA can happen via memory mapped commands but also through 16 dedicated event lines that notify the end of an operation.
The processing system runs at 330 MHz (worst case @0.72V) and the eFPGA has been optimized to run at 100 MHz in the same corner, although actual operating speed will depend on the application being mappeed on the eFPGA.
The name Arnold, comes actually from Arnold Schwarzenegger. The lead designer Davide says that just as Arnold Schwarzenegger was successful in multiple unrelated roles as an athlete, a movie star, an entrepeneur and a politician, the Arnold chip, thanks to the eFPGA, will be able to fulfil multiple roles as well.