The IIS Chip Gallery
Trikarenos (2022)
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by
| Application | Pulp |
| Technology | 28 |
| Manufacturer | TSMC |
| Type | Research |
| Package | QFN40 |
| Dimensions | 1414μm x 1414μm |
| Gates | 3 MGE |
| Voltage | 0.9 V |
| Power | 19.7 mW @250MHz |
| Clock | 250 MHz |
Trikarenos is an initial test platform for a fault-tolerant microcontroller architecture designed to tolerate radiation-induced faults. The SoC features a PULPissimo system with On-Demand Redundancy Grouping of three Ibex processor cores, either to enforce correct execution or enable high performance in independent mode. 8 banks of word-interleaved memory present a total of 256 KiB storage, featuring error-correcting codes (ECC) to allow for single error correction and double error detection for each 32-bit data word. Typical for a PULPissimo platform, the SoC also features some simple peripherals, such as UART, SPI, and a few GPIOs. An initial watchdog implementation is also featured to ensure correctable behavior even for uncorrectable errors. Furthermore, dedicated scan chains allow injecting faults in the spatially separated cores for testing, and custom registers enable easy access to the individual memory bits to insert faults without dedicated radiation test equipment.
A miniPULP system is added for dedicated vulnerability testing, spatially separated from the PULPissimo system. miniPULP features a minimal implementation of a triple-core lockstep microcontroller with two ECC-protected memory banks for a total of 32 KiB, two GPIOs, and some additional redundancy features.
The chip is named after a three-headed serpent column, Trikarenos. However, the logo on the chip with three ibex heads represents the three Ibex cores that make up the triple-core lockstep featured on Trikarenos.
Trikaneros is a radiation tolerant PULPissimo system. See also Cerberus.