The IIS Chip Gallery

Siracusa (2022)

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by

Manuel Eggimann, Alfio Di Mauro, Arpan Prasad, Davide Rossi, Francesco Conti

Main Details

Application	Pulp
Technology	16
Manufacturer	TSMC
Type	Research Project
Package	Baredie
Dimensions	4000μm x 4000μm
Voltage	0.6-0.8 V
Power	151 mW @ 0.65 V, 210 MHz
Clock	360 MHz

Description

Siracusa is a digital SoC for Extended Reality visual processing in TSMC16. It combines:

1. A general purpose cluster of 8 RISC-V digital signal processing cores with XpulpNN extensions
2. A large (36-core_ reconfigurable and cooperative Neural Engine (NEureka) with support for 3x3, 1x1 and depthwise convolutions with flexible weight precision (2-8bit) and 8bit activations
3. 4MB of SRAM and 4MB of non-volatile memory (NVM) tightly coupled to the accelerator for weight storage

Siracusa is a co-operation between ETH Zurich and Meta Reality labs. Read more about Siracusa on PULP Platform WWW site.

The name of the chip is a homage to the ancient Greek city of Siracusa, in eastern Sicily, that was the hometown of the famous mathematician Archimedes of Syracuse. Incidentally, it is also very close to the hometown of Alfio. The name of the NEureka accelerator is a pun on its function as a neural engine, combined with the legendary quote from Archimedes when he discovered his famous principle on water buoyancy: "Eureka! - I found it".

Related Publication

• Arpan Prasad, Moritz Scherer, Davide Rossi, Alfio Di Mauro, Manuel Eggimann, Jorge Tomas Gomez, Ziyun Li, Syed Shakib Sarwar, Zhao Wang, Barbara De Salvo, Luca Benini, "Siracusa: A Low-Power On-Sensor RISC-V SoC for Extended Reality Visual Processing in 16nm CMOS", IEEE 49th European Solid State Circuits Conference (ESSCIRC 2023), Lisbon, Portugal, 2023, pp. 217-220, DOI: 10.1109/ESSCIRC59616.2023.10268718