The IIS Chip Gallery
AES_double (2008)
Additional pictures below, click to see larger versions
by
| Application | Cryptography |
| Technology | 180 |
| Manufacturer | UMC |
| Type | Diploma Thesis |
| Package | PGA120 |
| Dimensions | 5000μm x 2500μm |
| Voltage | 1.8 V |
This project aimed at high-speed implementations of the Advanced Encryption Standard (AES) cipher on ASICs. The goal was to reach the highest throughput possible by using standard cells, and even further improvements in throughput with a new kind of cells based on pass-transistor logic (PTL).
First, the Rijndael algorithm has been implemented using several high speed strategies like iterative design decomposition and deep pipelining. Meanwhile, comparisons between PTL cells and standard CMOS logic cells have been conducted. The investigation of the results led to a new kind of hybrid logic (HL) cells that have been developed using both technologies, taking profit of the PTL speed and supporting it with the stability of the CMOS logic.
The fastest implementation involved six stages of pipelining inside each round of the AES core, allowing a simulated throughput of 100 Gbps with moderate increase in area and cost.
Due to the limited chip size for student projects, a smaller and slower version has been chosen and implemented once using the standard CMOS cells and once with the new hybrid logic cells.