The IIS Chip Gallery
Neo (2022)
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by
| Application | Pulp |
| Technology | 65 |
| Manufacturer | TSMC |
| Type | Research |
| Package | QFN64 |
| Dimensions | 3200μm x 2000μm |
| Gates | 2500 kGE |
| Voltage | 1.2 V |
| Power | 65 mW @200 MHz |
| Clock | 200 MHz |
Neo is the first design that integrates a Linux-capable RISCV core - the well-known Ariane (CVA6) - with an enhanced RPC DRAM memory controller for off-chip communication and peripherals to form an SoC capable of booting Linux. It is the first realization of this kind in TSMC65.
In addition, a new VGA controller allows to drive VGA displays, and its functionality has been proven by emulating the design on an FPGA before chip tapeout. The RPC controller is fully AXI4 compliant, which makes it stand as reusable IP that allows off-chip communication with 700 MiB/s bandwidth while preventing an explosion in the number of off-chip memory pins.
The name of the chip was supposed to be Neo Scarabaeus as a follow up chip to Scarabaeus which had a similar goal. The name was just a bit too long, and we ended up keeping the Neo part. Once the name stuck like that, the logo followed as well.