The IIS Chip Gallery
Shiva (1993)
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by
| Application | Communication |
| Technology | 1500 |
| Manufacturer | VLSI Tech |
| Type | Reserach |
| Package | PGA84 |
| Dimensions | 7600μm x 7600μm |
| Gates | 25 kGE |
| Voltage | 5 V |
| Clock | 65.5 MHz |
A direct-sequence spread-spectrum (DSSS) RAKE receiver chip (Shiva) for microcellular wireless communication systems was developed. In a DSSS system, signal bandwidth is spread by multiplying data with a psuedo-noise code sequence. The receiver recovers the original data by correlation with the synchronized spreading sequence and allows reocmbining signals from propagation paths with different delays.
The received signal passes through down converter, A/D Converter and matched filter before data correlation and demodulation are performed on-chip. The ASIC accepts code sequences from outside and is controlled by a DSP.
The receiver chip consists of six correlator arms, a data demodulator and a processor interface for control purposes. The correlator arms are used for inital code acquisition, code tracking and multipath data correlation. Each correlator arm integrates the product of incoming data samples with the code bots over an entire code length and can be programmed with an individual spreading code delay. The outputs are scaled and fed into the subsequent data demodulator. The correlator runs at 16.4 MHz.
The data demodulator part of the Shiva direct-sequence spread- spectrum RAKE receiver ASIC performs two tasks: (1) combining the data obtained from four of the correlator arms into a single data decision and (2) recovering the carrier phase of each parh and feeding it back to the data decision algorithm.
To facilitate experimentation with the prototype implementation, output is provided in a variety of formats:
In addition to these output formats, raw data (8-bit real, 8-bit imaginary) is also available by way of the DSP interface. The DSP furthermore controls the demodulation mode (BPSK,QPSK), the phase tracking speed and whether hard decisions are to be differentially coded.
The demodulator runs at 32.7 MHz and occupies the top block in the layout.