|Dimensions||2582.6μm x 1902μm|
The demand for high data rates and high resolutions remains the driving force behind the development of analog-to-digital converters (ADCs). While oversampling ADCs offer high resolutions at moderate bandwidths and flash converters are used to achieve very high conversion speeds, successive approximation register (SAR) converters allow within limits for a continuous trade-off between resolution and bandwidth. Pipelined ADCs have the potential for large bandwidths at considerable resolutions with sampling rates up to several hundreds of megasamples per second (MS/s), and thus offer an adequate solution especially for wireline communication systems.
The ongoing reduction of minimum feature sizes of CMOS processes presents new challenges to the design of converters. While the feasibility of low-resistance switches allows for higher settling speeds in switched capacitor applications, increasing leakage currents severely impact the achievable resolution. Wiring parasitics also begin to play an important role.
Contrary to the observed trend in many recent publications on pipelined ADCs with low supply voltages, the implemented chip aims at a high resolution. This is made difficult by signal-to-noise ratio degradation, caused by the reduced signal swing. Measurements confirm that the resolution of the realized ADC is well above 11.1 bits (effective) for sampling rates up to 50 MS/s, and exceeds 11.6 ENOB at lower signal frequencies at a supply voltage of 1.2 V.