The IIS Chip Gallery

Chimera (2025)

by

Lorenzo Leone, Moritz Scherer, Alfio Di Mauro, Gamze Islamoglu, Philip Wiese, Marian Verhelst, Xiaoling Yi, Ryan Antonio, Yunhao Deng, Lucas Huijbregts, Asmae El arrasi, Anteneh Gebregiorgis Motta Taouil, Said Hamdioui, Bas Ahn, Rick Luiken, Henk Corporal, Manil Dev Gomony, Marc Geilen, Sander Stuijk, Zerun Jiang, Beat Muheim, Luca Benini

Main Details

Application	Pulp
Technology	22
Manufacturer	GF
Type	Research
Package	PGA84
Dimensions	4000μm x 3000μm
Gates	1
Voltage	0.8 V
Power	10 pW @GHz mW
Clock	400 MHz

Description

Chimera is the first heterogeneous microcontroller unit template built on the Cheshire host architecture, featuring a 256KiB L2 memory island and five specialized clusters for DNN applications. As part of the CONVOLVE European project, Chimera integrates four Snitch-based clusters from KU Leuven,TU Delft, and TU Eindhoven, with the ITA accelerator from the PULP team serving as the fifth cluster for efficient Multi-Head Attention operations.

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