The IIS Chip Gallery

Mr.Wolf (2017)

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by

Antonio Pullini, Davide Rossi

Main Details

Application	Pulp
Technology	40
Manufacturer	TSMC
Type	Research Project
Package	QFN64
Dimensions	3200μm x 3200μm
Gates	1800 kGE
Voltage	0.8-1.1 V
Power	153 mW @ 1.1 V, 450 MHz
Clock	450 MHz

Description

After quite a bit of development the next generation of PULP systems are here. Mr. Wolf is an IoT processor using optimized RISC-V cores.

Some features:

• One cluster with eight 32bit RISC-V cores (RI5CY) supporting ICMF extensions.
• Two IEEE-754 compliant FPUs each shared by four cores.
• A minimal area RISC-V (zero-riscy) fabric controller in the SoC module that can be used for basic control operations
• Integrated LDO to generate all internal voltages
• 64 Kbyte TCDM + 512 Kbyte L2 Memory

Mr. Wolf features a 108uW fully retentive memory (512 kByte). The I/O subsystem is capable of transferring up to 1.6Gbit/s in less than 2.5mW. The 8-core compute cluster achieves a peak perfromance of 850 millions of 32bit integer multiply and accumulate per second (MMAC/s) 500 millions of 32-bit floating point multiply and accumulate per second (MFMAC/s). As well as an efficiency of 15 MMAC/s/mW and 9 MFMAC/s/mW.

Mr. Wolf continues our tradition of naming chips from characters from the movie Pulp Fiction by Quentin Tarantino. Mr. Wolf solves problems, and this is exactly what we believe this chip will do. An ultra-low power IoT chip that can be used in many different applications.

Related Publication

• Antonio Pullini, Davide Rossi, Igor Loi, Giuseppe Tagliavini, Luca Benini, "Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing", In IEEE Journal of Solid-State Circuits, vol. 54, no. 7, pp. 1970-1981, July 2019, DOI: 10.1109/JSSC.2019.2912307