The IIS Chip Gallery
Dustin (2020)
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by
| Application | Pulp |
| Technology | 65 |
| Manufacturer | TSMC |
| Type | Research |
| Package | QFN64 |
| Dimensions | 4000μm x 2500μm |
| Gates | 7 MGE |
| Voltage | 1.2 V |
| Power | 69.6 mW @166 MHz |
| Clock | 166 MHz |
Dustin is a test chip based on the PULP architecture, meant to push the performance and the efficiency of Mixed-Precision Quantized Neural Network (QNN) inference on extreme edge Internet of Things (IoT) devices. It consists of a tiny microcontroller system (called Soc) accelerated by a SIMD (single-instruction-multiple-data )/ MIMD (multiple-instruction-multiple-data) cluster of 16 cores.
Both cluster's and Soc's cores are furnished with the newest MPIC (Mixed-Precision-Inference-Core) core, which includes the xMPI SIMD processing extensions (RISC-V based) coupled with a software configurable status-based execution of the program.
Being a test chip, Dustin comes with a relatively small L2 memory size, which is 112 kB, while the L1 memory, shared among all the 16 MPIC cores of the cluster, is 128 kB in size, divided into 32 banks.
The novelty of this chip does not end here. Indeed, Dustin has also a software-configurable MIMD/SIMD cluster. The two modes can be conveniently selected by the programmer with very low execution latency. When the SIMD mode is active, only one core dispatches instructions, allowing to save energy in all those cases where the executing kernel is extremely regular in terms of instructions (let's think about matrix multiplication, convolution or loops of instructions). On regular kernels Dustin, in SIMD mode, can reduce the cluster energy consumption down to 40% with respect to the PULP-based classic MIMD mode.
Thanks to these features, Dustin wants to demonstrate to be a fully-programmable edge of Iot device to enable efficient parallel execution of computing-intensive kernels, such as convolutions, of modern QNNs that, to fit the tiny memory of IoT devices, always compress activations and weights to low bit-width and asymmetric (Mixed-precision) integer operands (even down to 4/2-bit).
Like most PULP chips, the SoC is furnished with several peripherals like JTAG, QSPI, I2C, I2S, Camera Interface, UART and a JTAG-based RISC-V debug specification compliant debug unit with full access to the main memory bus of the system.
The Soc of Dustin is designed to operate at maximum frequency of 166 Mhz (cores and L2 memory) as well as the cluster, while the peripheral clock frequency is 50 MHz.
The name Dustin comes from Dustin Henderson, a character from the TV series Stranger Things. The chip has a very unusual logo that it uses actually two metal layers for the logo. While this may look wasteful, consider that MPW runs are designed to be inclusive and contain all possible options. In this case using less metal layers would not result in a smaller, cheaper or better design. we just made the most fo available space. The logo looks pretty good on the chip, but it requires the right angle/light to see it properly.