Angelo Garofalo
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Designer for following chips
Publications related to the chips in the gallery
- Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Alfio Di Mauro, Luca Benini, Davide Rossi, "Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode", IEEE Transactions on Circuits and Systems I: Regular Papers, DOI: 10.1109/TCSI.2023.3254810
- Angelo Garofalo, Yvan Tortorella, Matteo Perotti, Luca Valente, Alessandro Nadalini, Luca Benini, Davide Rossi, Francesco Conti, "DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training", IEEE Open Journal of the Solid-State Circuits Society, vol. 2, pp. 231-243, 2022, DOI: 10.1109/OJSSCS.2022.3210082
- Mattia Sinigaglia, Luca Bertaccini, Luca Valente, Angelo Garofalo, Simone Benatti, Luca Benini, Francesco Conti, Davide Rossi, "ECHOES: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I2S DSP for Flexible Data Acquisition from Microphone Arrays", IEEE International Symposium on Circuits and Systems (ISCAS 2023), 21-25 May 2023, Monterey CA, USA, DOI: 10.1109/ISCAS46773.2023.10181862
- Francesco Conti, Davide Rossi, Gianna Paulin, Angelo Garofalo, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Vincent Huard, Olivier Montfort, Lionel Jure, N. Exibart, Pascal Gouedo, Mathieu Louvat, E. Botte, Luca Benini, "A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing", International Solid-State Circuits Conference (ISSCC 2023)