The IIS Chip Gallery
Fluffy (2025)
by
| Application | Pulp |
| Technology | 130 |
| Manufacturer | IHP |
| Type | Teaching |
| Package | QFN56 |
| Dimensions | 2235μm x 2235μm |
| Gates | 500 kGE |
| Voltage | 1.2 V |
| Power | 45.2 mW @50 MHz |
| Clock | 51 MHz |
Modern edge computing applications increasingly rely on efficient data movement to enable low-power artificial intelligence (AI) workloads. Many of these workloads involve vector and matrix operations, which, despite hardware acceleration, are often limited by memory bandwidth and data handling overhead.
To address this bottleneck, this project integrates a multi-head Data Movement Accelerator (DMA) engine into the Croc SoC, which serves as the base design for this VLSI 2 course. The foundation of this work is the iDMA engine developed by the PULP team, previously extended to support multi-head capabilities.
The chip, affectionally named Fluffy, tyakes inspiration from Hagrid's three-headed dog in Harry Potter and the Philosopher's Stone. Just like its namesake, our Fluffy has three heads, two read and one write head, making it particularly suited for accelerating memory-bound operations.
The multi-head DMA implementation accelerates vector operations, specifically addition, subtraction, multiplication, and AXPY. Our contribution involves adapting the iDMA architecture to the Croc user domain, resolving backend integration challenges, and demonstrating its impact through synthesis, place-and-route, and simulation.
By accelerating memory-bound operations, the enhanced DMA delivers up to a 9.75x speedup in relevant workloads without increasing design complexity too much, thereby improving both performance and energy efficiency. The main contributions of this project are:
The sources for the design can be found on the GitHub Repo for Fluffy.
This chip was designed as part of the VLSI design course at ETH Zurich which uses a (mostly) open source design flow for its exercises. Students are required to modify a Croc based SoC to improve its capabilities somehow to pass the course. This was one of the top-rated designs from the course and has been sent to manufacturing.
Other chips from this series include:
This design has received generous support from Leibniz Institute for High Performance Microelectronics through the BMBF project FMD-QNC (16ME0831).