Thomas Villiger
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Designer for following chips
Publications related to the chips in the gallery
- Jens Muttersbach, Thomas Villiger, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, "Globally-asynchronous locally-synchronous architectures to simplify the design of on-chip systems", IN proc. Twelfth Annual IEEE International ASIC/SOC Conference, Sep 1999, page: 317-321, DOI: 10.1109/ASIC.1999.806526
- Jens Muttersbach, Thomas Villiger, Wolfgang Fichtner, "Practical design of globally-asynchronous locally-synchronous systems", Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems, ASYNC 2000, page(s): 52 - 59, DOI: 10.1109/ASYNC.2000.836791
- Stephan Oetiker, Thomas Villiger, Frank K. Gurkaynak, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, "High resolution Clock Generators for Globally-Asynchronous Locally Synchronous Designs", In handouts of Second Asynchronous Circuit Design Workshop (ACiD 2002), Munich
- Thomas Villiger, Hubert Kaeslin, Frank K. Gurkaynak, Stephan Oetiker, Wolfgang Fichtner, "Self-Timed Ring for Globally-Asynchronous Locally Synchronous Systems", In proc. of 9th International Symposium on Asynchronous Circuits and Systems, ASYNC 2003, Vancouver, DOI: 10.1109/ASYNC.2003.1199174