The IIS Chip Gallery

Phoebe (2015)

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by

Michael Gautschi, Michael Schaffner

Main Details

Application	Pulp
Technology	65
Manufacturer	UMC
Type	Research
Package	QFN40
Dimensions	1252μm x 1252μm
Gates	600 kGE
Voltage	1.2 V
Power	22 mW @1.2V 100MHz
Clock	500 MHz

Description

This chip continues the tradition of the Moon series of small PULP chips that add various floating point operations to a cluster of 4 processors, and joins its sisters:

• Artemis
• Hecate
• Selene
• Diana

This chip is a four Or10n core mini PULP processing system with 32 kBytes of L2 memory, 16 kBytes of L1 shared TCDM memory organized into 8 banks and a total of 4 kBytes of instruction cache.

Phoebe is very similar to Selene and contains shared logarithmic number units. In this chip there are two shared LNUs:

1. one 32bit single precision LNU with a latency of 4 cycles
2. one vectorized LNU containing two 16-bit half precision LNUs with a latency of 2 cycles

There are also various improvements with respect to the LNU used in Selene:

• Support for trigonometric extensions in the LNU (sin, cos, atan)
• Support for fused multiply/divide add/sub operations (fma, fda, fms, fds)
• Support for vector LNU operations (add, sub, mul, div, sqrt, casts, trig, fma, dotp)
In total all LNUs occupy an area of 71 kGE.

We have used a multi-VT approach to reduce leakage currents in this chip. 24% of the gates are Low VT (fast), 29% are Standard VT (normal) and 47% are High VT (slow).

This chip continues the tradition of naming these chips after mythological characters that have a connection to the moon. Phoebe was one of the Titans, she is the grandmother of Artemis (through Leto) and Hecate (through Asteria). In some texts the name is also used in place of Selene, completing the cycle.

Related Publication

• Michael Schaffner, Michael Gautschi, Frank K. Gurkaynak, Luca Benini, "Accuracy and Performance Trade-offs of Logarithmic Number Units in Multi-Core Clusters", 23rd IEEE Symposium on Computer Arithmetic (ARITH 2016), Santa Clara USA, DOI: 10.1109/ARITH.2016.10