Felix Buergin
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Designer for following chips
Publications related to the chips in the gallery
- Flavio Carbognani, Felix Buergin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner, "Two-Phase Resonant Clocking for Ultra-Low-Power Hearing Aid Applications", In Proc. Design, Automation and Test in Europe, 2006. DATE '06., DOI: 10.1109/DATE.2006.243985
- Flavio Carbognani, Felix Buergin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner, "Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications", In. Proc. International Workshop on Power and Timing Modelling, Optimization and Simulation PATMOS 2005, DOI: 10.1007/11556930_46
- Flavio Carbognani, Felix Buergin, Luca Henzen, Herbert Koch, Hovig Magdassian, Christoph Pedretti, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, "A 0.67-mm2 45uW DSP VLSI implementation of an adaptive directional microphone for hearing aids", Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005., DOI: 10.1109/ECCTD.2005.1523080
- Felix Buergin, Flavio Carbognani, Martin Hediger, Robert Meyer-Piening, Rafael Santschi, "Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm", 43rd ACM/IEEE Design Automation Conference, 2006, DOI: 10.1109/DAC.2006.229289
- Flavio Carbognani, Felix Buergin, Daniel Kraehenbuehl, Frank Zuercher, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner, "Low-power constant-coefficient FIR filtering in a hearing aid application", 8th International Conference on Solid-State and Integrated Circuit Technology, ICSICT '06, Page(s): 1637 - 1639, DOI: 10.1109/ICSICT.2006.306357
- Felix Buergin, Flavio Carbognani, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, "29% Power Saving through Semi-Custom Standard Cell Re-Design in a Front-End for Hearing Aids", 49th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS '06, Page(s): 610 - 614, DOI: 10.1109/MWSCAS.2006.382137
- Flavio Carbognani, Felix Buergin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner, "Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, July 2008, Vol: 16 , Issue:7, page(s): 830 - 836, DOI: 10.1109/TVLSI.2008.2000457
- Flavio Carbognani, Simon Haene, Manuel Arrigo, Claudio Pagnamenta, Felix Buergin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner, "A 0.25um 0.92 mW per Mb/s Viterbi decoder featuring resonant clocking for ultra-low-power 54 Mb/s WLAN communication", IEEE Custom Integrated Circuits Conference, CICC '07, Page(s): 451 - 454, DOI: 10.1109/CICC.2007.4405771